Design and Realization of Multi-port Register File based on Schematic

Abstract

In cpu design, the register file is a necessary device which save the instruction and data. In this paper, we propose a design method for multi-port register file design in the environment of single-cycle CPU system based on the MIPS instruction set and according to the characteristics of multi-port register file, and the Schematic is introduced in order to speed up the development cycle. Furthermore, we discuss the consideration and operational principle of design and realization in detail. The simulation results for the part constructed by FPGA are also presented. In this example which provides the learning and design innovation for other circuit designed. KEYWORD: Multi-port register file; Schematic; Programmable Logic Device; FPGA International Conference on Industrial Technology and Management Science (ITMS 2015) © 2015. The authors Published by Atlantis Press 1373  R0 is connected to 0. When reading R0, will always be 0; when writing R0, no action, no effect. So, if some instruction need 0 as one operand, R0 is used as the source data register.  R31 is used as default purpose register when instruction such as JAL, BLTZAL, BLTZALL, BGEZAL, BGEZALL do not specify the purpose register.R31 is used as general register. Of course, according to the need to increase or decrease and extend the register number, for example, the designing method of the register file composed of 64 registers is same, only the scale is lagrer. Of course, according to the need to increase or decrease and extend the register number, for example, the designing method of the register file composed of 64 registers is same, only the scale is lagrer. 2.1 Use Schematic to Design the Register File Schematic editor input method is similar to the traditional method of electronic design, that is, to draw the circuit diagram that can complete specific function by EDA software graphic editor interface. Schematic diagram consist of the logic device (symbols) and connection wire, the logic device in diagram may be pre-function module in EDA software library, such as the and gate, trigger, a variety of function modules including 74 series device[3]. Even there has the similarly IP function module. EDA software QuartusII provides a powerful, intuitive, convenient and flexible operation schematic design function, At the same time it is equipped with a variety of richer component library for the various needs, and it also provides the multilevel design function of the schematic input, so that users can design the more large-scale circuit system[4]. The register file makes up of five modules with three levels, the module under lowermost level is D trigger, the middle level module includes five bits address coder, 32-bits register and 32-to-1 multiplexer, the upper level module is the multi-port register file module[5]. Design adopts the method combining the act of modeling and structure, first using the way of the act modeling to establish the module under lowermost level, then using the way of the structure modeling to establish the higher circuit design, the following is which all the modules under level are introducted separatily. 2.2 References Address Coder Model A coder is an important device in the combination logical circuit, if 32 registers need be accessed, which will change five input into 25, that is multioutput ends with 32 outputs, in all input changing combinations, each output is one which only is once, so output ends are the combination which is the input variable smallest. Because the writing action of the register file must be controlled by writing control signal, the coder with ENA enable input end may be designed, just which make ENA enable input end as a writing control signal, that is when ENA equal 0, the coder do not work, its outputs are 0; when ENA equal 1, the coder works normally, which can carry out writing operation to the register file. Also which names the enable input end as high-level availability when input end ENA equal 1 and it works normally[6]. The following is the logical expression based on logic truth table, in which N[4..0] is the number register of the writing chunnel, ENA is the writing control signal, E[31..0] is the register of the writing chunnel. E[0]=ENA· ] 0 [ E · ] 1 [ E · ] 2 [ E · ] 3 [ E · ] 4 [ E E[1]=ENA·E[0]· ] 1 [ E · ] 2 [ E · ] 3 [ E · ] 4 [ E