Design and power analysis of 4 × 4 semiconductor ROM array with row decoder and column decoder at 32, 22 and 16 nm channel length of MOS transistor

Abstract

In this work, the design and power consumption analysis of NOR based 4 × 4 semiconductor read-only-memory (ROM) array has been presented. In this study, row decoder and column decoder has been considered in order to retrieve the data from ROM array. All the circuits are designed using nanodimensional metal oxide semiconductor (MOS) transistor. The average power consumption across the ROM array structure has been reported for the MOS transistors with channel length of 32, 22 and 16 nm. Selecting the row lines and column lines using row decoder and column decoder, data written inside the ROM array has been retrieved. In order to verify the data inside the ROM array, simulated waveforms are presented. Overall design and power consumption analysis of the ROM array in nano regime has been analyzed with the help of Tanner SPICE (T-SPICE) tools. It is seen that as power supply voltage VDD increases the average power consumption across the ROM structure also increases. This indicates that for low power design the value of VDD needs to be downscaled. Comparison of the average power consumption for MOS transistors having channel length 32, 22 and 16 nm has been reported.