Design and Power Analysis of 16×16 SRAM Array Employing 7T I-LSVL

Abstract

Static Random access memories are the significant building blocks in applications like Cache memories, Processors and Portable gadgets. Hence there is need for SRAM Memory. But the design of SRAM is involved at the rate of increased power consumption. So the challenge is requirement of Low Power & energy efficient Memory design. In this paper an effort is made to design and simulate a Low power 16x16 SRAM Memory Array employing 7T I-LSVL SRAM Cell. Peripheral components of entire 16x16 SRAM Array like Sense amplifier, Row decoder, Column decoder are designed. The Power Consumption of proposed 16x16 SRAM Memory Array is 18.3mW which is an improvement of 8.66% [2]. The proposed design work is carried using Cadence Virtuoso tool employing standard library gpdk 180nm.