Design and Performance Comparison of CNTFET-Based Binary and Ternary Logic Inverter and Decoder With 32 nm CMOS Technology

Abstract

This paper attempts to compare ternary and binary logic gate design using CMOS and carbon nanotube (CNT)-FETs technology. Ternary logic is an effective approach over the default binary logic design technique because it allows to define one more voltage level which is VDD/2 and it also allows a circuit to be simple in design and energy efficient due to its property of reduction in circuit overhead such as interconnects and chip area. A CMOS and CNTFET-based ternary logic gates and arithmetic circuit design has been proposed to implement and compare binary and ternary logic design based on CMOS and CNTFET. The main objective is to compare the CMOS and CNTFET results and verify the advantages of CNTFET technology. The proposed CNTFET technique combined with ternary logic provides an usable performance, improved speed and reduces propagation delay characteristics in circuit such as inverter and decoder. Simulation results of proposed designs using H-SPICE are observed and shown that the proposed ternary logic gates consume significant less delay than the CMOS gates implementations. In realistic digital application, the proposed design of ternary logic compared with binary logic results in over 95% reductions in terms of the consumption of propagation delay.