Design of CNFET based ternary comparator using grouping logic

Abstract

This paper presents a design of ternary magnitude comparator based on the CNFET (Carbon Nanotube Field Effect Transistor) ternary logic gates. Ternary logic is a promising alternative to conventional logic design because of its energy efficiency. This energy efficiency is achieved due to the reduced circuit overhead for ternary logic when compared to the conventional binary logic. The comparator design is based on prefix based design and combines ternary and binary logic gates for optimized implementation. The proposed comparator has been implemented and simulated using SPICE. Simulations results indicate that the proposed 1-bit comparator consumes 0.65μW power and has a delay of 21ps. The simulation results for comparators with different operand lengths are also presented.