Abstract
This paper proposes the structure of a vertical PNPN single gated feedback field-effect transistor (vertical FBFET) and investigates its performance using a TCAD simulator. The performance of the device is investigated against variations in a few geometrical and process parameters. The device exhibits an ultra-steep switching characteristic with a minimum subthreshold swing of 0.03 mV/dec and a high ON/OFF current ratio of ∼1011. Subsequently, the hysteresis characteristic of the vertical FBFET is analyzed against variation in interface trap charges at Si and Al2O3 interfaces. Due to the presence of negative/positive interface trap charges at silicon and Al2O3 interface, the memory window is enlarged/reduced from 1.1 V to 1.21 V/0.96 V respectively. The vertical FBFET also shows a wide variation in the memory window for channel length and temperature variations.
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