Abstract
Multipliers play an extremely important role when we are concerned with arithmetic operations and digital signal processing. Therefore, the execution time for these multipliers should be high in order to speed up the calculation and get faster results. Hence, designing a multiplier suiting all the possible parameters such as processing speed, the fabrication area and also the power consumption is important. In multipliers, adders play a very crucial role as they are the basic building blocks for any arithmetic operations. Thus array multipliers having varied adder architectures like carrying ripple adder (RCA), carry look ahead (CLA), and few configurations of carry save adder (CSA) like CSA, conventional CSA with half adder, CSA with the last stage RCA and CSA with the last stage CLA were designed and analysed for performance parameters like maximum combinational path delay, total power consumption and area utilisation using Xilinx ISE platform. The designed multipliers were targeted for Spartan 6 XC6SLX9 CSG324 speed-2 with 16 MB flash space, 100MHz oscillator, 8 LEDs and 4 switches for user-defined purposes.
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