Design and optimization of sequential counters using a novel reversible gate

Abstract

Low power consumption is a vital issue for digital circuits in today's technological era. Hence reversible logic plays a significant role in designing low power digital circuits. In the existing literature, a lot of research has been done on reversible sequential circuits. In this paper author presents the design of asynchronous and synchronous digital counters using a novel reversible gate. This design intends to optimize the counter in terms of number of reversible gates, delay and garbage outputs and thus complexity of the circuit reduces. Hence this optimized design will significantly strengthen the performance of the sequential counters concerning size and power utilization.