Efficient Designing Approach of Different Synchronous Cyclic Code Counters by Sequential Circuit Elements of a Novel Reversible Gate

Abstract

Reversible logic is widely being considered as the probable logic design style for implementation in modern nanotechnology, optical computing and quantum computing with least impact on physical entropy as because of its less power dissipation as well as distinct output assignment for each distinct input. A reversible circuit maps each output vector into a unique input vector, and vice versa. This paper proposes a new reversible gate. This paper represents various classical operations of this proposed reversible gate. It also represents different sequential circuit elements of reversible gate and its application in designing different synchronous cyclic code counters. The proposed reversible gate is better for designing reversible counter compared to those gates reported in the literature in terms of garbage output, quantum cost and complexity of gates. These synchronous reversible counters give the initial threshold to construct the more complex structure having reversible sequential circuits as a primary component and which can implement more complex operations using quantum computers. Since the output of a sequential circuit depends not only on the present inputs but also on the past input conditions, the construction of sequential elements using reversible logic gates is quite complex than that of a combinational circuit. This paper proposes reversible D flip flop, JK flip flop, T flip flop and also represents two types of 4 bit synchronous cyclic code decade counter (SCCDC) and a 4 bit synchronous gray cyclic code counter (SGCCC) using proposed reversible T flip flop. A comparison between these designs in terms of garbage output, number of gates, constant input and total logical calculation also has been made.