Design and optimization of double-gate SOI MOSFETs for low voltage low power circuits

Abstract

With the growing use of portable and wireless electronic systems, design of high performance, low-voltage, low-power digital devices and circuits has become an important concern for VLSI applications. The double-gate (DG) fully-depleted (FD) silicon-on-insulator (SOI) MOSFET has an ideal subthreshold slope, high drive current and superb short channel effect immunity, which makes it very attractive in low-voltage, low-power, and high-performance CMOS designs. In this paper, by solving the Poisson equation, we propose a general model which has been verified by SOI-SPICE simulations. Based on this model, DGSOI MOSFETs are compared with conventional single gate FD SOI (SGSOI) MOSFETs, and the design and optimization of DGSOI MOSFETs in terms of circuit delay, power dissipation and power delay product are presented. In our analysis, we focus on FD DGSOI transistors without volume inversion, where the classical method is still valid.