Design and operation of a 550 kbit enhanced density 3 μm bubble memory chip

Abstract

A 550 kbit bubble memory chip that employs standard 3 μm bubbles and an enhanced density concept has been designed, fabricated and characterized at 100 kHz. The chip employs conventional 16 μm period swap-in/replicate-out gates, and 10.5 μm X and Y circuit periods in folded minor loops. Worst case overall write/read and minor loop propagation margins of 13 Oe and 14.5 Oe respectively, are obtained with a 45 Oe drive field. Also, minor loop longevity high and low end margin slopes of −0.25 Oe/decade and 0.2 Oe/decade, respectively are achieved. It is concluded that it is possible to almost double the storage density of 3 μm bubble devices while still maintaining adequate device performance.