Bubble memories for microcomputers and minicomputers

Abstract

An analysis has been made of the utilization of 65,536 bit bubble memory chips in small memory hierarchies for microcomputers and minicomputers. Two basic chip organizations were considered. One chip organization was assumed to be equivalent to that of Ypma, Gergis, and Archer with a conventional major minor loop configuration. The other organization considered employed a major-minor loop configuration in which the minor loops were broken into two segments to facilitate stacking and implementation of multilevel hierarchies as suggested by Tung, Chen, and Chang. The analysis shows that a near optimum organization for 65,536-bit chips with segmented minor loops consists of 64 minor loops of 1024 bits with each minor loop broken into a 64-bit segment and a 960-bit segment.