Abstract
Carbon nanotube field-effect transistor (CNTFET) refers to a field-effect transistor that utilizes a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. Since it was first demonstrated in 1998, there have been tremendous developments in CNTFETs, which promise for an alternative material to replace silicon in future electronics. Carbon nanotubes are promising materials for the nano-scale electron devices such as nanotube FETs for ultra-high density integrated circuits and quantum-effect devices for novel intelligent circuits, which are expected to bring a breakthrough in the present silicon technology. A Static Random Access Memory (SRAM) is designed to plug two needs: i) The SRAM provides as cache memory, communicating between central processing unit and Dynamic Random Access Memory (DRAM). ii) The SRAM technology act as driving force for low power application since SRAM is portable compared to DRAM, and SRAM doesn't require any refresh current. On the basis of acquired knowledge, we present different SRAM's designed for the conventional CNTFET. HSPICE simulations of this circuit using Stanford CNTFET model shows a great improvement in power saving.
Highlights
The power consumption has become an important consideration on the VLSI system design and microprocessor as the demand for the portable devices and embedded systems continuously increases [1, 2]
While seeking for solutions with higher integration, performance, stability, and lower power, carbon nanotube (CNT) has been presented for next-generation Static RAM (SRAM) design as an alternative material in recent years [11]-[15].This paper proposes a novel 4T, 5T, 6T, 7T, 8T, 9T and 10T SRAM cells based on Carbon nanotube field-effect transistor (CNTFET) to reduce dynamic write-power and to improve the read cycle at the cost of minimal increase of cell area
Access to the cell is enabled by the word line (WL) which controls the two access transistors M5 and M6 which allow the access of the memory cell to the bit lines: ‘BL’ and ‘BLbar’
Summary
The power consumption has become an important consideration on the VLSI system design and microprocessor as the demand for the portable devices and embedded systems continuously increases [1, 2]. CNTFET among other new materials is promising due to the unique one-dimensional band-structure which reduces backscattering and makes near-ballistic operation. Exceptional electrical properties such as high speed, high-K compatibility, chemical stability, low SCEs have provided CNFETs with. While seeking for solutions with higher integration, performance, stability, and lower power, carbon nanotube (CNT) has been presented for next-generation SRAM design as an alternative material in recent years [11]-[15].This paper proposes a novel 4T, 5T, 6T, 7T, 8T, 9T and 10T SRAM cells based on CNTFET to reduce dynamic write-power and to improve the read cycle at the cost of minimal increase of cell area
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