Design and modeling of PLL-based clock and data recovery circuits with periodically embedded clock encoding for intra-panel interfaces

Abstract

This study investigates the design issues of a phase-locked loop (PLL)-based point-to-point (P2P) high-speed interface with periodically embedded clock encoding (PECE). Interfaces of this type are the mainstream serial links for 4K2K or higher resolution applications in the display industry. Early works mainly focus on delay-locked loop (DLL)-based or Hogge-type CDR implementation, while this work presents a compact and low-power PLL-based clock and data recovery (CDR), and discusses the effects of error transfer, spread-spectrum clock (SSC) tolerance, and the embedded-clock period on the CDR performance and bandwidth design. Both discrete-time (DT) and continuous-time (CT) analyses in this paper give insight into the folded jitter transfer property in a PECE CDR system. The proposed high-speed interface is implemented in a 0.18μm 1.8V/13.5V high-voltage process, and verified on 4K2K liquid crystal display (LCD) panels. The equivalent data rate of the interface is 2GHz, and the power consumption is 18.4mW.