2.5-Gb/s/ch 17-Channel Parallel Clock and Data Recovery Circuit

Abstract

A 2.5 Gb/s/ch parallel clock and data recovery (CDR) circuit is designed for the SFI-5 interface. To avoid the reference clock in the conventional approaches, a phase locked loop (PLL) is used to recover the clock from the received data. To make the parallel recovered data bit-synchronous, a delay locked loop (DLL) is used to make retime at the center of data eye but at the rising edge of the recovered clock. A double-channel CDR circuit was fabricated by TSMC's standard 0.18 mum CMOS process. With two parallel 231-1 pseudorandom bit sequences (PRBS) input, the rms jitter of the recovered 2.5 GHz clock is 2.4 ps. The rms jitter of the recovered 2.5 Gb/s data is 3.3 ps.