Abstract
In this manuscript, a novel physically doped single gate F-shaped tunnel FET is simulated and optimized. The designed configuration is well optimized and analyzed for different source thickness, source length, drain length with different lateral tunneling lengths between the source edge and gate dielectric. Also, we optimized some stand-points like threshold voltage, ION to IOFF current ratio, ambipolar conduction range, sub-threshold swing and various capacitance to rectify the analog/RF performance of single gate F-shaped TFET. Regarding this, we concurrently optimize the lateral tunneling length between source and gate with optimization of source thickness. The variation in lateral tunneling length, the potential and strength of electric field at fixed Vgs voltage is varied which leads to effective change in the ON-current, average sub-threshold swing, and turn ON-voltage. Another side, as well as the source thickness vary, the electric field variation takes place near the edge of source, which leads to variation in the ON-current and ON-voltage. The performance parameters of single gate F-TFET is compared with single gate L-TFET, which is the incentive of this submitted work. The optimized single gate F-TFET have 0.30 V turn ON-voltage with 7.4 mV/decade average sub-threshold swing and high Ion/Ioff ratio approx 1013. Besides, a significant reduction in parasitic capacitance is beneficial to enhanced RF performance with better controllability on channel.
Highlights
T O get the better of MOSFET, Tunnel FET (TFET) has been brought in as an auspicious candidate for a low power application because its sub-threshold swing (SS) can be scaled down than 60 mV/dec [1], [2]
This section edifies the impact of the shape of source and channel regions on the performance of physically doped TFET
A new SG-F-TFET is designed and its fundamental physics of devices and working principle are investigated in detail using the 2D TCAD simulator
Summary
T O get the better of MOSFET, Tunnel FET (TFET) has been brought in as an auspicious candidate for a low power application because its sub-threshold swing (SS) can be scaled down than 60 mV/dec [1], [2]. The Si-based single gate Tunnel FET experience very low ION with high ambipolar conduction because of approximately same band-to-band (B2B) tunneling on both drain/channel and source/channel interface [3]. Dual-Gate TFET (DG-TFET) was introduced for better channel controllability to improve the ION current but again the ambipolar conduction is a major issue [4]. A novel device structure for low power application named as single gate F-shaped TFET (SG-F-TFET) has been proposed and optimize which consists highly doped source enclosed by a lightly doped silicon region. With the help of the electric field crowding effect, the SG-F-TFET is supposed to minimize VON as the source thickness is decreased [14], [15]. 2D TCAD tool is used to simulate and analyses the analog/RF properties of the SG-F-TFET
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