Improving the performance of dual-k spacer underlap Double Gate TFET

Abstract

In this paper, the effect of dual-k spacer is investigated on underlap Double-Gate TFET (DGTFET) for low-k and high-k gate dielectrics. Simulation study shows that the position of dual-k spacer junction must be aligned with metallurgical junction (tunneling junction) between source and channel region for improved performance. DGTFET structure is optimized to improve the performance metrics such as on-current (Ion), off-current (Ioff) and subthreshold swing (SS) for low-k and high-k gate dielectrics. An optimized DGTFET shows impressive improvements in Ion and average SS when compared to their conventional DGTFET structures. Optimized DGTFET with SiO2 and HfO2 as gate dielectric shows improvements in Ion by 15874.03% and 525.71%, average SS by 46.17% and 25.15% respectively when compared to their conventional counterpart. Proposed optimization is useful in enhancing the performance of dual-k spacers based DGTFETs.