Abstract
A signal generator with adjustable frequency, phase and duty cycle is designed in this paper. The design of this signal generator is based on the technology of direct digital synthesis (DDS).The classic structure of DDS is presented and its principles are introduced in detail. The key modules of the design such as phase accumulator and pulse width processing are implemented by verilog HDL language. With suitable FPGA, the designed signal generator and all modules of the design are simulated successfully in Quartus II.
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