Design and Implementation of Safety Logic with Fine Impulse Test System for a Nuclear Reactor Shutdown System

Abstract

500MWe sodium cooled Prototype Fast Breeder Reactor (PFBR) is in the advanced stage of construction at Kalpakkam (Tamilnadu), INDIA. PFBR is provided with two independent and fast acting shutdown systems (SDS). Each SDS consists of sensors, signal processing electronics, safety logic (SL) system, drive mechanisms and neutron absorber rods (NARs). The purpose of SDS is to reduce the reactor power rapidly during abnormal events which could otherwise lead to catastrophic situations. During an abnormal event, the NARs are rapidly inserted into the reactor core within a second, in an operation called scram. An automatic and rapid shutdown of a nuclear reactor in response to an abnormal event is known as scram. Safety Logic (SL) system continuously monitors the state of various reactor scram parameters (i.e. the events requiring prompt reactor shutdown), and performs 2-out-of-3 (2oo3) voting on each scram parameter thus enables/disables the flow of current in the Electro-Magnet (EM) coils, which are holding the NARs. During an abnormal event (For example: rapid and uncontrolled increase in neutron flux inside reactor core, core temperature crossing its set limits etc.) SL system initiates reactor shutdown action by de-energizing the EM-Coils causing all the NARs to drop into the reactor core under gravity. The scram parameters are triplicated to achieve high availability and reliability. The design of SL system was carried out using VHDL and targeted to Simple Programmable Logic Devices (SPLDs) and Field Programmable Gate Array (FPGAs) devices. The probable faults in digital logic devices are stuck-at faults (i.e. stuck-at-'0' or stuck-at-'1'). For SL System, stuck-at-'0' is a safe condition whereas stuck-at-'1' is a dangerous condition (i.e. during an abnormal event SL may not be able to initiate reactor shutdown action). Hence, to diagnose safe and dangerous failures in SL system, an online test facility i.e. Fine Impulse Test (FIT) system has been provided. FIT system injects short duration test pulses periodically at the input stage of SL system in various combinations and verifies the propagation of these test pulses by monitoring the output stage of SL system. FIT system detects safe and dangerous failures in SL system, ensures its availability periodically. FIT system has also been implemented using VHDL and targeted to FPGA devices. This paper discusses the design and implementation of Safety Logic with Fine Impulse Test (SLFIT) system for one of the reactor shutdown systems of PFBR. This paper focuses on the design methodology, design implementation and qualification testing of the SLFIT system.