Design and Implementation of PLL with Dead Zone-Less Low-Power Phase Frequency Detector

Abstract

This project introduces a Phase-Frequency Detector (PFD) that includes a dedicated circuit for removing the dead zone. This design utilizes Pass Transistor Logic (PTL) and Delay Cells (DCs) to effectively address this issue. Additionally, a Low-Pass Filter is integrated into the system and connected with charge pump, employing a technique that replaces resistors with transistors, thereby significantly reducing the overall circuit area. Furthermore, a Phase-Locked Loop (PLL) serves to eliminate the dead zone and significantly reduce the circuit's size. This project aims to advance circuit design methodologies by enhancing performance and minimizing area requirements.