Design and Implementation of Multi Channel Read-Out and Level 2 Storage for Time Measurement Chip

Abstract

This paper describes the design, implementation, and testing of a multichannel read-out and level 2 buffering circuit for a time measurement chip, L2I. L2I version 1.0 interfaces a four-channel version of the Time Measurement Cell (TMC) with the next level in the front-end electronics chain, the Data Collection Chip (DCC) for read-out of the SDC straw tracking detector. The chip was implemented as a standard cell design, except for a full-custom SRAM block, and fabricated in a 1.2 /ira n-well CMOS process. The total area of the chip including pads and off-chip driving circuitry is 12 ram2. Power consumption during full-speed operation is 12 mW. High level simulation of the circuitry was performed using Verilog HDL, and detailed timing simulations were carried out with Hspice. The chip was tested on an HP82000 IC test-station and was found functional with a minor design error in the control path.