Design and Implementation of Low Power and High Speed Autocorrelator and CORDIC Architectures for OFDM

Abstract

Abstract—OFDM systems are currently being widely used in 4G and UWB communication systems. OFDM system consisting of IFFT and modulator increases the complexity of hardware implementation. In this paper, design and implementation of Autocorrelator and CORDIC algorithm for OFDM is discussed for optimized power and delay. Autocorrelator is used for frame detection and carrier frequency offset estimation. The CORDIC is used to estimate the frequency offset and to calculate the division in the channel estimation algorithm. HDL and test bench is developed to simulate and verify the functionality of both the modules. The design is implemented on Xilinx FPGA and semicustom ASIC targeting 130nm technology. The autocorrelator design is optimized to consume 5684 cells (13969.5μm² of area) with power reduced to 78.7μW. The CORDIC architecture occupies 2288 μm² total cell area. The total area comprising of both the modules is 2558 μm² consuming 12.05μW.