Abstract
Based on the xc7k325tffg900 FPGA chip of Xilinx Company and combining the actual hyperspectral image compression task requirements, the calculating speed and compression efficiency of the algorithm module are optimized. In the design of the prediction module in this article, the two-clock solution is used to solve the problem that the algorithm speed is restricted due to the feedback of the weight update. And the RTL-level design is implemented on the FPGA. CCSDS 123.0-B-1 hyperspectral image lossless compression algorithm is achieved. The system uses block compression to deal with the data source to avoid the entire system compression data errors caused by a certain pixel compression error. So the system’s Error Resilience ability is improved. Finally the compressed code stream is decoded. The decompressed image is consistent with the raw one, which verifies the correctness of this design.
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