Design and Implementation of High-Speed Clock Recovery Circuits Based on FPGA

Abstract

According to the problem that the traditional clock recovery method based on FPGA can not recover the clock of higher frequency NRZ (Non-return to zero) serial data. This paper proposed a clock recovery design that adjusts the output clock earlier or later constantly according to the phase relationship between the input data and the feedback clock. The proposed design can be implemented on the FPGA without the higher operating frequency requirement meets the demand of middle and low version FPGA clients. The circuits implemented on FPGA has been downloaded to the Xilinx Virtex5 XC5VSX50T FPGA after behavioral simulation and post-route simulation, the debugging results verified that the proposed design is effective and realizable for clock recovery of higher frequency NRZ data and realizable for FPGA.