Design and implementation of high performance and area efficient square architecture using Vedic Mathematics

Abstract

Now a days, an efficient arithmetic operations are important to accomplish the high performance. In every one of these applications, multiplier is an important arithmetic operation. Usually multipliers are utilized to evaluate the square operand. A square operation is faster than a multiplication. This paper proposes a high performance and area efficient square architecture using Anurupya Sutra of Vedic Mathematics. The proposed method is efficient method, which divided the large magnitude number into smaller magnitude numbers and concatenated smaller magnitude numbers. The proposed architecture is synthesized and simulated using Vivado design suite 2018.3 and implemented on Kintex-7 FPGA board. The results revealed a high performance and area efficient compared to a well-known prior art multipliers.