Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic Mathematics on FPGA

Abstract

High speed and area efficient multiplier architecture plays a vital role in Arithmetic Logic Unit (ALU) design, especially when it comes to low power implementation of Central Processing Units, Microprocessors and Microcontrollers. In this paper, we propose a novel, area efficient and high speed architecture to implement a Vedic mathematics multiplier based on Urdhva Tiryakbhyam methodology. The same was utilized within an ALU and its performance was compared with the existing ALU designs. It was found that the proposed methodology is around 2 times faster than the existing ALU architectures. Also a significant 3% decrease in area, in comparison with existing designs was obtained. The proposed algorithm was designed and implemented using Verilog RTL on a Xilinx Spartan 3e FPGA and compared with other algorithms. The results prove that the proposed architecture could be a great boon for high speed and low area based processor design.