Abstract
Advanced Encryption Standard is the most popular cryptographic security algorithm used for data protection and transmission. The paper proposes an implementation of the AES new Mix- Column operation. In this paper, an enhanced Mix- Column is designed for AES decryption through Very Large Scale Integration (VLSI) System design environment. In AES Mix-Column, large number of logic gates used to perform the multiplication of input stage bytes (output of shift row) and fixed defined state bytes. In order to decrease this problem, the redundant function of Mix-Column is eliminated and re-designed in this paper. Proposed model of Mix-Column minimizes 25% of logic gates compared with previous work. Further, the proposed Mix-Column of AES decryption achieves by improving the performance of area, delay and power consumption. The implementation of the transformation is optimized and increase speed.
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