Abstract
The southbound protocol of Software Defined Networking (SDN) enables the direct access into SDN switches which accelerates the innovation and deployment of network functions in the data plane. Correspondingly, SDN switches that support the new southbound protocol and provide high performance are developed continuously. Therefore, there is an increasing need for testing tools to test such equipment in terms of protocol correctness and performance. However, existing tools have deficiencies in flexibility for verifying the novel southbound protocol, time synchronization between the two planes, and supporting more testing functions with less resource consumption. In this paper, we present the concept of CPU & FPGA co-design Tester (CFT) for SDN switches, which provides flexible APIs for test cases of the control plane and high performance for testing functions in the data plane. We put forward an efficient scheduling algorithm to integrate the control plane and the data plane into a single pipeline which fundamentally solves the time asynchronization between these two planes. Due to the reconfigurable feature of our proposed pipeline, it becomes possible to perform different testing functions in one pipeline. Through a prototype implementation and evaluation, we reveal that the proposed CFT can verify the protocol correctness of SDN switches on the control plane while providing no-worse performance for tests on the data plane compared with commercial testers.
Highlights
Software-Defined Networking (SDN), decoupling the control plane from the data plane, enables the invocation and evolution in the development of the network
Our paper proposes the concept of CFT, which is an open CPU and Field Programmable Gate Array (FPGA) co-design Tester for Software Defined Networking (SDN) switches
The CFT reconfigurable pipeline we implemented is composed of hardware modules which support different testing functions such as traffic generation and traffic monitoring
Summary
Software-Defined Networking (SDN), decoupling the control plane from the data plane, enables the invocation and evolution in the development of the network. This brings the problem of clock asynchronization because the clock reference used in the control plane and the data plane are different, which introduces errors in time-related tests such as the correctness detection on the Barrier message Based on these inaccurate testing results, researchers or vendors are hard to determine whether SDN switches meet the expected requirements. The experiments revealed that with CFT, users are able to develop a wide range of test cases through provided APIs regarding the correctness and the performance while keeping no-worse accuracy compared to commercial testers and similar flexibility in comparison with software-based test tools. We make the following contributions: We propose the CFT, a CPU & FPGA co-design Tester, which takes full advantage of hardware and software to enable precise and flexible test for SDN switches.
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