DESIGN AND IMPLEMENTATION OF ADDRESS GENERATOR FOR WIMAX DEINTERLEAVER ON FPGA

Abstract

This Paper enumerates efficient method of address generator for WiMAX Deinterleaver using verilog coding. It is a low-complex, high speed and resource efficient method because it eliminates the requirement of floor function. The use of an internal multiplier of FPGA and the sharing of resources for quadrature phase-shift keying (QPSK),16-quadrature-amplitude modulation (QAM), and 64QAM modulations along with all possible code rates makes our approach to be novel and highly efficient when compared with conventional look-up table-based approach. The proposed approach exhibits significant improvement in the use of FPGA resources.