Abstract
Recent wireless communication standards such as 3GPP-LTE, WiMax, DVB-SH and HSPA incorporates turbo code for its excellent coding performance. The interleavers involved in these turbo encoder and decoder play vital role in their performance. In this paper, we have proposed a linear feedback shift register (LFSR) based interleaver for turbo code. The proposed interleaver is compared with existing quadratic permutation polynomial (QPP) and almost regular permutation (ARP) interleavers. The investigation on the hardware implementation of these interleavers were carried out in terms of area and power consumption, and maximum frequency of operation. Hardware implementations were performed in Field Programmable Gate Array (FPGA), as well as in Application Specific Integrated Circuit (ASIC) using 130 nm complementary metal oxide semiconductor (CMOS) technology.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
