LFSR Schema Using CMOS VLSI Technologies—Design, Implementation and Comparative Analysis

Abstract

Linear Feedback Shift Register (LFSR) is fundamentally a shift register capable of generating random sequences. It is a Pseudo-Random Number Generator (PRNG) whose randomness is driven through the linear feedback function governed by the primitive polynomial. LFSR has many real-time use cases but is not limited to cryptographic keys, NONCE, fast digital counters, data whitening, ATSC digital broadcasting standards, Intelsat business service, CDMA cellular telephony, Ethernet scrambles, etc. Due to the enormous growth in the VLSI industry, optimised LFSR designs were constructed to fit inside the chip’s silicon substrate to perform the indented tasks. The Complementary Metal Oxide Semiconductor (CMOS) technique is largely adopted over the globe for the design and implementation. This work investigates the effect of LFSR design over two different CMOS technologies, namely 90 nm and 180 nm, through the pre-layout and post-layout simulations. Further, the results have been compared among themselves. Fascinatingly, LFSR using 90 nm occupies a very less area footprint of 90.07 μm2 and 0.04371049 W of power consumption in a Cadence Virtuoso environment. The area occupancy of 90 nm LFSR is 29.43% less than the 180 nm LFSR, which shows the impact of technology mapping. In addition, the proposed LFSR design is compared with the existing LFSR designs of various technologies, and the results ensure the consistency of the CMOS-based LFSR.