Design and Implementation of 6-T SRAM using FINFET

Abstract

Abstract: SRAM is designed using conventional CMOS tech- nology to store data in memory. A lot of devices, including logic and memory, are having different issues as a result of the channel being lost of control. These include low leakage current, high power consumption, and short channel effects, which raise production costs and lead to significant changes in characteristics and decreased dependability. It is advised to employ FINFET based SRAM cells rather than traditional CMOS ones as a result of these problems. One of the primary elements that must be decreased in order to increase the stability of SRAM cellsis thought to be power dissipation and leakage currents. The amount of power dissipation and leakage currents can be de- creased using a variety of low power methods. These include the Self Controllable Voltage Level (SVL) technique, Power Gating, Stacking technique, Variable Threshold CMOS (VTCMOS), and Multi Threshold CMOS (MTCMOS). Here, we suggest designing a FINFET SRAM cell using the 28nm technological approach andcomparing its dynamic power consumption and stability to thatof the 8T FINFET SRAM cell. Every simulation is carried out using the Cadence Virtuoso Tool.