Abstract
Adders play a vital role in the digital signal processing systems. The design of 32-bit adders is of high importance because 32-bit architecture is common and widely used in many digital systems and processors. In this paper, the design and the implementation of various 32-bit adders like Ripple Carry Adder (RCA), Carry Increment adder (CINA) and Carry bypass adder (CBYA) for different full adder cells is done using the Verilog HDL. The results are obtained by executing Verilog code in Xilinx 14.5 ISE for the Spartan 3E family device with speed grade −5.
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