Design and fabrication of a 1.2 kV GaN‐based MOS vertical transistor for single chip normally off operation

Abstract

We report a novel design to achieve normally off, high voltage power switch using an “all‐GaN” vertical MOS‐gate transistor (MOSVFET). In this structure, two MOS gates were formed vertically on the sidewalls of the pillar, whose opposite ends were connected to the source and drain of the device. The design space and associated performance based on 2D drift‐diffusion model is discussed highlighting the trade‐off between blocking voltage (Vbl), on resistance (Ron), and threshold voltage (Vth). An optimized device structure was proposed with more than 1.2 kV blocking capability and normally off behavior. With proper design of the drift region thickness and doping, the corresponding Ron was as low as 2.8 mΩ cm2. The role of key parameters such as bulk GaN mobility, channel mobility, gate to gate distance (Lgtg) and gate length (Lg) on the Ron, Vbl, leakage current, and Vth were also examined. The effect of mobility on the device performance and the role of the bulk GaN material was analyzed utilizing the model to create a comprehensive design space for achieving low‐loss switching.