3-D Simulation of Novel High Performance of Nano-Scale Dual Gate Fin-FET Inserting the High-K Dielectric TiO2 at 5 Nm Technology

Abstract

The evolution of integrated circuit is based on the miniaturization of dimension in the transistor Mosfet, this reduction causes the undesirable effect: short channel effects (SCE) and hot carrier effect, the principal goal is to search for a device which can minimize this effects, thus, in this work we proposed a new device for the dual gate DG-FinFET with TiO2 material for smaller gate length Lg = 5 nm by using the TCAD-SILVACO simulator. Additionally, we explain the electrical characteristics of this device on various parameters such us: threshold voltage Vth, subthreshold slope (SS), the on-current (Ion), the off-current (Ioff), Ion/Ioff current ratio, the DIBL (drain induced barrier lowering), and the electrical field E. The results show that our structure gives excellent electrical characteristics. It requires the use of high-k dielectric of gate TiO2 and to the shorter gate length (Lg). Furthermore, the decreasing of the electrical field along the channel proves the suppressing of the hot carrier effect; we examine also the effect of variation of gate length (Lg) on this parameter. We obtained the following results: our simulation is improved for the smaller gate length Lg = 5 nm than (6, 8, 10 and 12) nm. So we noticed that the proposed device is the most compatible for increasing the performance of device (the reliability, the lower power and speeder circuit), also the TiO2 material is the best dielectric of gate with combination of metal gate TiN for the future of nanoscale device.