Design and Evaluation of On-chip DCT accelerators based on Novel Approximate Reverse Carry Propagate Adders

Abstract

Reverse carry propagate full adders have shown significant performance benefits over other approximate full adder architectures, which is attributed mainly to the engineered reverse path of carry output, thereby the approximate sum output bit does not anymore depend on the the combinatorial function of preceding carry generated bits. The paper proposes two new performance-efficient approximate full adders configured to propagate carry in reverse order. In addition, a novel Tri-Split Hybrid Adder (TSHA) is introduced by adding another split inside the Bi-Split Hybrid Adder (BSHA) to increase the parallelism and leverage the performance and accuracy benefits of two different reverse carry adders. TSHA exhibited the average percentage improvement (percentage improvement for the best Figure of Cost design) of 51%(62%), 10%(11%), 3%(4%), and 55%(66%) towards performance, energy, area, and energy-delay-product (EDP) respectively, when applied across 8, 12, 16, 20, 21, and 24 bits of approximation in a 32-bit adder subsystem, with respect to 32-bit exact full adder (FA) based on Ripple carry adder design. The efficiency of proposed approximate adders including TSHA was investigated for designing On-Chip Discrete Cosine Transform (DCT) accelerator unit adopted for the JPEG image compression module. The DCT designed compression block offered a maximum of 40% performance the benefit with acceptable accuracy and no significant degradation in the image quality.