Design and Evaluation of Clocked Differential Adiabatic Logic Families for Low Power Applications

Abstract

In this paper, clocked differential adiabatic logic families, namely, Clocked CMOS Differential Adiabatic Logic (CCDAL) and Clocked Differential Cascode Adiabatic Logic (CDCAL) pertinent to low power applications have been presented. Charge recovery operation of these circuits are realized by the use of complementary two phase sinusoidal power signals. CCDAL uses clocked control transistor in addition to the differential CMOS logic structure which makes it suitable for higher frequency operation. Compared to the existing charge recovery circuits, CCDAL achieves reduced floating nodal output problem resulting in improved drivability and circuit robustness. CDCAL a variant of CCDAL has also been presented which displays enhanced frequency over CCDAL. The feasibility of operating these logic families at a system level design has been evaluated through design of a digital FIR filter which could be used in magnetic disk drive applications. A 4-tap 6-bit FIR filter has been designed using 90nm CMOS technology library and simulations are carried out using industry standard Cadence® Virtuoso tool. The simulation results prove that proposed adiabatic FIR filter achieves significant energy savings compared to its pipelined static CMOS logic counterpart.