Design and characterisation of 16×1 parallel outputs SPAD array in 0.18 um CMOS technology

Abstract

The design, simulation, fabrication, and characterisation of a silicon single photon avalanche diode (SPAD) array with integral quenching and discriminator circuits is presented. The array is a 16×1 parallel output SPAD array which comprised active quenched SPAD circuit in each pixel, and was fabricated in a UMC 0.18μm CMOS process. The SPADs were operated in the Geiger mode where the applied reverse bias voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RB</sub> ) is greater than the breakdown voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> ) at 11.03 V. A digital circuitry to control the SPAD array and perform processing the data provided by it was designed in VHDL and implemented on an FPGA chip. At room temperature, the dark count was found approximately 12875 counts per second (cps) for most of the 16 SPAD pixels and the dead time was estimated to be 40 ns. The apparent detection probability (ADE) from LED with λ= 470 nm was 17.4% at 1.5 V above V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> .