Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies

Abstract

Cellular automata (CA) have received significant attention in VLSI design for the inherent architectural advantages of modularity, cascadability, simplicity and localized interconnections. In this paper, we have designed FPGA fabric aware CA circuit topologies with a built-in bidirectional scan chain to facilitate fine-grained fault localization of any faulty logic element configured for circuit realization, without increase in logic resources or critical path delay. The scan path arrangement may also be used for seeding the CA with the desired initial state. The generation of circuit description files has been completely automated which further facilitates to single out the exact faulty logic element (if any) on which the circuit has been configured. The proposed architectures outperform the state-of-the-art error detection and fault localization techniques tailored for FPGA implementations both in terms of area and speed.