Abstract
This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance CL varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-µm CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375× drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3° phase margin (PM), while consuming 24.0-µW quiescent power at 1.0-V nominal supply voltage.
Highlights
The single-stage amplifier used to be one of the strongest candidates for precise analog signal processing when old CMOS technologies were employed because of its high-speed and inherent good stability characteristics
Expanding the report in [31], this paper provides the analysis and design insights for a low-power three-stage amplifier capable of driving the pF-to-nF capacitive load
The damping factor control frequency compensation (DFCFC) technique presented in [10] aims to
Summary
The single-stage amplifier used to be one of the strongest candidates for precise analog signal processing when old CMOS technologies were employed because of its high-speed and inherent good stability characteristics. Like [20] and [21], either an active zero or a wide-bandwidth scalar is embedded in the multistage amplifier to extend the non-dominant pole frequency for driving an extremely large capacitive load These techniques can achieve better small-signal performance by increasing the product of load capacitor value and unit-gain frequency. The Q-factor of the complex-pole pair is controlled by the local feedback loop adaptively, which improves the frequency response and shortens the transient settling time In this design, 375× capacitive load drivability is realized for the proposed amplifier.
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