Design and analysis of low power single ended 8T SRAM ARRAY (4×4) at 180nm technology

Abstract

In embedded memories as the feature size is decreasing continuously. The demand of low power design has increased. In this paper analysis has been performed on conventional 6T SRAM cell and proposed single ended 8T SRAM cell. Here the proposed 8T SRAM cell has the advantage of low power consumption ad high read static noise margin. The paper also includes SRAM cell arrays of both 6TSRAM cell and proposed single ended SRAM cell. The array comprises of address decoder, sense amplifier. The results shows that 8T SRAM array has the advantage of low power dissipation during read and write states over the array of 6T SRAM cell. The simulations are performed on Tanner EDA tool at 180nm technology.