Design and Analysis of Low Power and High-Speed Dynamic Comparator with Transconductance Enhanced in Latching Stage for ADC Application

Abstract

The increasing demand for low voltage, power efficient, high-speed analog-to-digital converters (ADCs) results in the improvement of speed and power of regenerative dynamic comparator. In this paper, a dual-tail dynamic comparator is used with two extra transistors in the latch stage. These extra transistors help in the increase of transconductance of the latch stage, which helps decrease the delay of the proposed comparator. Mathematical analysis is done for the proposed architecture; this gives the idea of reducing the delay of the comparator with an increase in the transconductance of the comparator. The simulation and layout of the proposed comparator are done on the Cadence software with 90[Formula: see text]nm CMOS technology. This proposed design is simulated with a 2[Formula: see text]GHz clock frequency at supply voltage of 1[Formula: see text]V. The proposed architecture consumes a power of 39.19[Formula: see text][Formula: see text]W and a delay of 143.12[Formula: see text]ps at 1[Formula: see text]V supply voltage, 5[Formula: see text]mV input difference voltage and 0.9[Formula: see text]V common mode voltage. The Monte Carlo simulation of the proposed architecture for power, delay, power delay product (PDP) and offset is also demonstrated in this paper. Process corner analysis is done for power, delay and PDP.