Design and analysis of inductors for 60 GHz applications in a digital CMOS technology

Abstract

RFIC designers of on-chip transceivers for 60 GHz applications face the trade-off between lumped and distributed design techniques, due to the on-chip wavelength of approximately 3 mm. This paper demonstrates that the lumped approach is favorable for realizing 60 GHz inductive components in digital CMOS technologies. Advantages in area consumption, Q-factor and the range of achievable component values are shown using simulations and measurements. Simulations of lumped inductors using the electromagnetic field solver HFSS are compared with measurements and different topologies for the lumped inductor are investigated and compared. The measurement results reveal that a planar unshielded topology yields the best inductor quality for 60 GHz circuits in a digital CMOS technology.