Abstract
In this project, we are designing a standard library cell with 90nm technology using GNU/Electric with MOCMOS technology. The library cell consists of 24 cells with each cell having the following views: Icon, Schematic and Layout. The standard library cell includes Basic Gates, Adder circuits, Flip-flops, Latches and Multiplexers. The parameters: Rise Time, Fall Time and Area for all these cells are calculated and listed in a table. Area of each cell in this library is compared with 180nm (CMOS Cells) and 300nm (MUDD Library) technologies. Simulation of each cell is done using LT-SPICE software. GDS file is generated for these cells and 3D view of the layouts is also shown.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
