Abstract
We report design and analysis of full-chip ESD protection solution for high-voltage (HV) mixed-signal ICs in a BCD30V technology by mixed-mode ESD simulation involving integrated process, device, circuit and layout co-design. The full-chip HV ESD protection scheme includes both I/O and power clamp ESD protection. Mixed-mode ESD simulation technique enables pre-Si ESD design optimization and prediction. ESD measurements confirm full-chip HV ESD protection of >4.5KV for the whole chip. This design technique can be applied to practical full-chip HV ESD protection circuit design for mixed-signal ICs in various HV BCD technologies.
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