Abstract
The paper outlines the utmost importance of energy-efficient devices for IoT applications and recommends adual edge-triggeredTSPC flip-flop in fully-static mode at 45nm technology with low supply rail carried out in CMOS using MENTOR GRAPHICS tool.The proposed flip-flop proved to be energy efficient compared to traditional double and single edge-triggered flip-flops in terms of latency, power, the figure of merit and area for IoT applications. A comparison of two types of dual-edge triggered flip-flops are analyzed concerning the mentioned performance metrics and deduces the best flip-flop for IoT applications. Clock overlap issues are turning down in dual edge-triggered TSPC flip-flopcompared with a conventional dual edge-triggered flip-flop in full static modeand allow stringent operation at 1V supply rail thatdelivers1.14uW power, 0.60fJ figure of merit and 531.99ps latency at 45nm CMOS.
Highlights
In a recentscenario,theInternet of Things (IoT) is the most emerging area in the era of healthcare and smart environments
This section entitles the simulations carried out in the MENTOR GRAPHICS tool, cons that are observed in AND-OR logic, pros by using transmission-gate MUX, comparative analysis of both the circuits at circuit level in terms of several parameters, like, Power, Speed, Figure of Merit, etc
The simulation wascarried out using the MENTOR GRAPHICS tool using 130nm, 90nm, 45nm CMOS process with VDD= 1V at 27OC temperature for both AND-OR logic& transmission-gatebased MUX latches are mentioned in figures 1 & 2
Summary
In a recentscenario,theInternet of Things (IoT) is the most emerging area in the era of healthcare and smart environments. TSPC performs the flip-flop operation with low power, delay and high clock speed [8] [9].
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