Abstract

Compressors are the fundamental components in multipliers to accumulate and reduce partial product stages in a parallel manner. This study presents several architectures for low-power 4-2 and 5-2 compressors, which are based on the proposed circuits of the full-swing and non-full-swing XOR gates in carbon nanotube field effect transistor (CNTFET) technology. The CNTFET technology has been chosen because of its unique electrical and mechanical features. The proposed circuits are investigated in terms of process, voltage and temperature variations, delay, power dissipation, energy, power-delay product (PDP) and transistor count. All the proposed and referenced designs are simulated using an HSPICE tool in a 32 nm CNTFET Stanford technology model. The results show that the proposed circuits have less PDP and power consumption than the previous work. The proposed compressors have the lowest PDP, achieving 5.8%–41.9% improvement.

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