Design and analysis of differential multiphase DLL for jitter and power optimization

Abstract

Phase detector (PD) and voltage controlled delay line(VCDL) is a main element in delay locked loop (DLL), the power optimized DLL is to generate multiple time/phase delay for different applications such as signal synchronization, VLSI applications and clock and data recovery. The performance of DLL depends upon Locked time, power consumption, time jitter and lock range. The main objective of this research is to design low power consumption, less locked time and less time jitter circuit. Jitter is the randomly variation in the period and phase of the clock signal. In the recent time, increasing the clock frequency, the time period of signal becomes very small due to that amount of jitter can be tolerated. The schematic is designed and simulated in cadence virtuoso analog design environment at 90nm CMOS technology with operating frequency range 100MHz to 1GHz. At 100MHz, the rms jitter with 1V supply is 4.653ps and power consumption is 132.7µW.