Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers

Abstract

The network switches and routers require both high-speed and large-capacity packet buffers. However, existing packet buffer architectures have the problems of speed scaling and flow number scaling limitations. To address the two problems simultaneously, this paper proposes a parallel hybrid SRAM/DRAM architecture for per-flow buffering in high-speed switches and routers. Tail SRAM and head SRAM are used to apply per-flow buffering for packet aggregation, so that the middle DRAM is accessed in a larger granularity and the DRAM's bandwidth utilization is improved. To mitigate the flow number scaling limitation, a dynamic memory allocation with hard timeout (DMA-HT) memory management algorithm is designed. The key idea of DMA-HT is that the memory space is dynamically allocated for the newly arrived flows, and a hard timeout is assigned for each queue. After a specific period of time, the memory space is freed, so that the SRAM space is efficiently utilized by the most recently active flows. A queuing system is used to model the proposed method, and theoretical analysis is performed to optimize the timeout value. With the derived formulas, multiple performance parameters are quantitatively analyzed, and the optimal timeout can be obtained. Both numerical results and simulations show that the proposed architecture can and reduce packet loss rate and average delay significantly compared with previous solutions with the same SRAM capacity.