Abstract
This paper presents the design of a 3.3V CMOS switched-current (SI) second-order sigma-delta modulator for A/D converters intended for radio front-end applications. The effects of non-ideal behaviours of the building blocks on the total performance of a SI double-integrator sigma-delta modulator (DISDM) were analysed and simulated by means of multi level (SpectreHDL-level, transistor-level) and mixed level simulations. The implementation of a SI DISDM concerning the practical issues is discussed. A second-generation cascode SI integrator was optimized to meet the desired speed and to diminish the non-ideal errors. The SI DISDM can operate at the sampling rate of 80MHz and over based on the parasitic-extracted transistor-level simulations.
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